Designing analog circuits

ABSTRACT

According to an aspect of an embodiment, a method of designing an analog circuit may include selecting multiple analog components for a circuit. The method may also include ordering the analog components. The method may also include determining at least one pareto-optimal design point for a parameter of each analog component. The pareto-optimal design point for each analog component may be based on a performance metric, the parameter for the respective analog component, and constraints resulting from pareto-optimal design points for analog components ahead of the respective analog component within the ordering of the analog components.

FIELD

The embodiments discussed herein are related to analog circuit design.

BACKGROUND

Analog circuit design has become more and more complex as transistorsand other analog circuit components have decreased in size, therebyallowing more and more analog components to be included within a singlecircuit. To optimize the design of a circuit with various analogcomponents, various trade-offs between different parameters of thevarious analog components may be analyzed. For example, the parameterswithin an analog circuit may include the size of an inductor, acapacitor, and/or a transistor. Changing one or more of the parametersof the analog components within a circuit may change the output of thecircuit. To determine parameters that result in a satisfactory oroptimal design, a circuit designer may use an analog circuit modelingtool using transistor level abstractions to explore the entire designspace of the analog components of the circuit.

To use the analog circuit modeling tool, the circuit designer may selectcircuit specifications for the analog components and/or the circuit andinput the circuit specifications into the analog circuit modeling tool.The circuit specifications may include information such as the maximumpower usage, maximum jitter, minimum bandwidth, among others. The analogcircuit modeling tool may use global design techniques to search withinthe entire design space of the analog circuit at a transistor levelabstraction for an optimal or satisfactory design point that satisfiesthe circuit specifications. Global design techniques typically analyzenumerous design points to determine an optimal or satisfactory designpoint. Large amounts of time may be used to perform the analysis ofnumerous design points, especially when each design point requires along analysis.

The subject matter claimed herein is not limited to embodiments thatsolve any disadvantages or that operate only in environments such asthose described above. Rather, this background is only provided toillustrate one example technology area where some embodiments describedherein may be practiced.

SUMMARY

According to an aspect of an embodiment, a method of designing an analogcircuit may include selecting multiple analog components for a circuit.The method may also include ordering the analog components. The methodmay also include determining at least one pareto-optimal design pointfor a parameter of each analog component. The pareto-optimal designpoint for each analog component may be based on a performance metric,the parameter for the respective analog component, and constraintsresulting from pareto-optimal design points for analog components aheadof the respective analog component within the ordering of the analogcomponents.

The object and advantages of the embodiments will be realized andachieved at least by the elements, features, and combinationsparticularly pointed out in the claims.

It is to be understood that both the foregoing general description andthe following detailed description are exemplary and explanatory and arenot restrictive of the invention, as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

Example embodiments will be described and explained with additionalspecificity and detail through the use of the accompanying drawings inwhich:

FIG. 1A illustrates an example analog circuit with analog components;

FIG. 1B illustrates an example graph of a pareto-optimal front for ananalog component in the analog circuit of FIG. 1A;

FIG. 2 is a block diagram of an example designing system for optimizinganalog circuits;

FIG. 3 is a flow chart of an example method of designing analogcircuits;

FIG. 4 illustrates an example circuit that may be designed using themethod of FIG. 3; and

FIG. 5 is a flow chart of an example method of designing analogcircuits, all arranged in accordance with at least some embodimentsdescribed herein.

DESCRIPTION OF EMBODIMENTS

Some embodiments described herein may include a method of designing ananalog circuit. In particular, some embodiments described herein mayinclude a method of designing an analog circuit using one or more levelsof abstraction higher than a transistor level of abstraction. The higherlevels of abstraction for each component within the analog circuit maybe based on one or more pareto-optimal design points and/or apareto-optimal front for the respective component. Using thepareto-optimal design points and/or the pareto-optimal front for therespective components, a pareto-optimization of the circuit may also beobtained.

Embodiments of the present invention will be explained with reference tothe accompanying drawings.

FIG. 1A illustrates an example analog circuit 150 with analogcomponents, arranged in accordance with at least some embodimentsdescribed herein. The analog circuit 150 may include a first analogcomponent 160 and a second analog component 170. In some embodiments,the first and second analog components 160, 170 may be simple transistorlevel components, such as a transistor, resistor, capacitor, inductor,diode, or some other transistor level components. In other embodiments,the first and second analog components 160, 170 may be complex analogcomponents that include one or more transistor level components, such asan op-amp, amplifier, charge pump (CP), voltage controlled oscillator(VCO), multiplexer, demultiplexer, phase locked loop (PLL) that includesa VCO and a CP, or other complex analog component or some combination ofcomplex analog components. In some embodiments, one of the first andsecond analog components 160, 170 may be a simple transistor levelcomponent and the other of the first and second analog components 160,170 may be a complex analog component.

The first and second analog components 160, 170 may have parameters thatmay be adjusted. In some embodiments, the parameters may becharacteristics of the first and second analog components 160, 170 thatmay be changed. For example, if the second analog component 170 is atransistor, the parameters of the transistor may include the width,length, doping concentration, or other parameter or characteristic thatmay be adjusted or changed. As another example, if the first analogcomponent 160 is a VCO, the parameters of the VCO may include the widthand/or length of a transistor within the VCO or other parameters of atransistor and a size of a capacitor or inductor within the VCO or otherparameters of the capacitor or inductor.

For the same analog component, depending on how the parameters of theanalog component are defined, the parameters may be different. Forexample, if the first analog component 160 is a VCO, a parameter mayinclude a quality factor of the VCO. The quality factor of the VCO maybe determined based on set values of components within the VCO, such asthe size of transistors, inductors, and capacitors within the VCO. Inthis example, the quality factor of the VCO may be changed or adjusted.Based on the selected quality factor, the size of the transistors,inductors, and capacitors within the VCO may change as well. In someembodiments, the size of the transistors, inductors, and capacitorswithin the VCO are changed based on a change of the quality factor andare not changed independent of the quality factor. In contrast, in someembodiments, the parameters of the VCO may be the size of transistors,inductors, and capacitors within the VCO. In these and otherembodiments, the size of the transistors, inductors, and capacitorswithin the VCO may each be changed independently.

The values assigned to all the parameters belonging to an analogcomponent may be referred to as a design point. Thus, a design point mayinclude a number of values equal to a number of parameters for an analogcomponent. A set of all possible design points for the analog componentmay be referred to as a design space for the analog component. Forexample, if the first analog component 160 is a transistor withparameters of width, length, and doping concentration, a single designpoint for the first analog component 160 may be the first analogcomponent 160 having a width at a first value, a length at a secondvalue, and a doping concentration at a third value. Varying the width,length, or doping concentration of the first analog component 160 maychange the design point of the first analog component 160. All of thevarious combinations of different widths, lengths, and dopingconcentrations may be the design space for the first analog component160. In some embodiments, the analog circuit 150 may have constraintsthat may limit the design space for the first analog component 160. Forexample, if the analog circuit 150 had a minimum power requirement, thewidth of the first analog component 160 may have a limited range ofpossibilities to meet the minimum power requirement thereby limiting thedesign space for the first analog component 160.

The first and second analog components 160, 170 may also have one ormore performance metrics. A performance metric may be a measurablequality of the first and second analog components 160, 170 that isaffected by the value of the parameters of the first and second analogcomponents 160, 170. Some example performance metrics for various analogcomponents may include power, area, bandwidth, tuning range, noise,phase noise, power supply noise, jitter, among others. For example, ifthe first analog component 160 is selected as a transistor, theperformance metrics of the first analog component 160 may include power,bandwidth, or some other performance metric. In these and otherembodiments, a parameter of the first analog component 160, such as awidth of the first analog component 160, may affect the power orbandwidth of the first analog component 160.

In some embodiments, one or more of the first and second analogcomponents 160, 170 may have multiple performance metrics. For example,the second analog component 170 may be a VCO and may have performancemetrics that include jitter, quality factor, power, area, tuning range,noise, phase noise, power supply noise, as well as other performancemetrics. In some embodiments, one or more of the performance metrics ofan analog component may be dependent on one or more of the otherperformance metrics of the analog component. When performance metrics,such as first and second performance metrics of an analog component, aredependent, an increase or decrease in the first performance metric mayresult in a corresponding increase or decrease in the second performancemetric. For example, if the second analog component 170 is a VCO thathas performance metrics of power and jitter, an increase in the powermay result in reduced jitter and a decrease in power may result inincreased jitter. Thus, a change in a parameter that affects power mayresult in a change in jitter in the second analog component 170.

In some embodiments, different parameters and different values for theparameters may affect different performance metrics differently, even ifthe performance metrics are dependent. For example, at some designpoints for an analog component, a change in a value of a parameter ofthe analog component may result in bettering first and second dependentperformance metrics of the analog component. At another design point forthe analog component, a change in a value of the parameter of the analogcomponent may result in bettering one of the first and secondperformance metrics and worsening the other of the first and secondperformance metric. Design points that result in making one performancemetric better and another dependent performance metric worse when achange in a parameter occurs may be referred to as pareto-optimal designpoints. Multiple pareto-optimal design points may be referred to as apareto-optimal front.

FIG. 1B illustrates an example graph 100 of a pareto-optimal front 130for the first analog component 160 in the analog circuit 150 of FIG. 1A,arranged in accordance with at least some embodiments described herein.The graph 100 includes a first axis 110 that may indicate a value of afirst performance metric of the first analog component 160. The graph100 also includes a second axis 120 that may indicate a value of asecond performance metric of the first analog component 160. Both of thefirst and second performance metrics may be optimized by having lowervalues. The graph 100 illustrates a design space 142 for the firstanalog component 160 that is bounded by the pareto-optimal front 130.The graph 100 further illustrates various pareto-optimal design points132, 134, 136 along the pareto-optimal front 130. Each of thepareto-optimal design points 132, 134, 136 may correspond to the valuesof the parameters that resulted in the values of the performance metricsin the graph 100.

In the illustrated embodiment of FIG. 1B, two performance metrics havebeen combined to obtain a pareto-optimal front 130. More generally,multiple performance metrics may be combined to obtain a pareto-optimalsurface. For example, 3, 4, 5, or more performance metrics may becombined to obtain a pareto-optimal surface.

With combined reference to FIGS. 1A-1B, and by way of example only, thefirst analog component 160 may be a VCO with the first performancemetric being power and the second performance metric being jitter. Insome embodiments, having low power and low jitter may be ideal for thefirst analog component 160. The pareto-optimal front 130 may thusrepresent the best obtainable values for low power and low jitter forthe first analog component 160 and trade-offs between the power andjitter. As illustrated in the graph 100, trade-offs between the powerand the jitter may include having higher power to obtain lower jitterand having higher jitter to obtain lower power. Various parameters forthe first analog component 160 may include the sizing of transistors,inductors, and capacitors within the first analog component 160.Numerous design points may exist for varying values of the parametersthat are not on the pareto-optimal front 130. In some embodiments,selecting values of parameters for a design point on the pareto-optimalfront 130 may allow for better optimization of the first analogcomponent 160 and the analog circuit 150.

Referring again to FIG. 1A, changing a design point of the first analogcomponent 160 may place constraints on the second analog component 170.For example, the first analog component 160 may include a CP and thesecond analog component 170 may include a VCO. The first analogcomponent 160 may have parameters that include the width of a transistorwithin the first analog component 160. The width of the transistor mayaffect the output impedance of the first analog component 160. Theoutput impedance of the first analog component 160 may affect theselection of parameters in the second analog component 170 whenoptimizing performance metrics of the second analog component 170. Thus,adjusting the parameters of the first analog component 160 may placeconstraints on the second analog component 170 that affect the selectionof parameters in the second analog component 170 and thus theperformance metrics of the second analog component 170.

In some embodiments, the first and second analog components 160, 170 maybe modeled using parameterized low-level models, such as transistorlevel modeling. Low-level models may simulate some or all of thephysical properties of each of the first and second analog components160, 170 to determine performance metrics for each of the first andsecond analog components 160, 170. Alternately or additionally,low-level models may also use empirical models based on non-linear orlinear equations to simulate each of the first and second analogcomponents 160, 170. In some embodiments, the low-level models may bereferred to as SPICE models. Different low-level models may be used foreach of the first and second analog components 160, 170 depending on theselected parameters and/or performance metrics for each of the first andsecond analog components 160, 170.

In some embodiments, the first and second analog components 160, 170 maybe modeled using parameterized high-level models. The high-level modelsof the first and second analog components 160, 170 may be at a higherlevel of abstraction than the low-level models described herein. In someembodiments, the high-level models may be based on a hardwaredescription language. For example, the high-level models may begenerated using Verilog or Very High Speed Integrated Circuit HardwareDescription Language (VHDL). Different high-level models may be used foreach of the first and second analog components 160, 170 depending on theselected parameters and/or performance metrics for each of the first andsecond analog components 160, 170.

FIG. 2 is a block diagram of an example designing system 200 fordesigning analog circuits, arranged in accordance with at least someembodiments described herein. The designing system 200 may include anordering module 208, a constraint module 210, a pareto-front module 214,a validation module 220, a circuit simulation module 224, a database230, an interface module 240, a memory 242, and a processor 244.

The interface module 240 may be configured to receive data concerning acircuit under design that includes analog components. For example, insome embodiments, the interface module 240 may be configured tointerface with a person to receive data concerning the circuit to bedesigned. Alternately or additionally, the interface module 240 may beconfigured to interface with a device to receive data concerning thecircuit to be designed.

The data received by the interface module 240 may identify digitaland/or analog components included within the circuit and/or connectionsbetween the digital and/or analog components. The data may also includeone or more parameters and/or one or more performance metrics for eachof the analog components. Alternately or additionally, the data mayinclude predetermined values for each of the selected parameters.Alternately or additionally, the data may include predeterminedconstraints for the circuit and/or one or more of the individual analogcomponents. Alternately or additionally, the data may include one ormore performance metrics for the circuit. Alternately or additionally,the data received by the interface module 240 may include low and/orhigh-level parameterized models for each of the analog components.Alternately or additionally, the data received by the interface module240 may include models of the digital components within the circuit.Alternately or additionally, the data received by the interface module240 may include design criteria for the circuit.

The interface module 240 may send the data to the other modules withinthe designing system 200. For example, the interface module 240 may sendthe data identifying the digital and/or analog components and theconnections between the digital and/or analog components to the orderingmodule 208. The interface module 240 may also send the receivedpredetermined constraints to the constraint module 210 and the receivedperformance metrics, parameters, high-level and low-level models andother information to the pareto-front module 214 and the circuitsimulation module 224.

The interface module 240 may include and/or may be coupled to one ormore input devices and/or output devices to facilitate receiving dataabout the digital and/or analog components from the person and/oroutputting circuit design results to the person. The one or more inputand/or output devices may include, but are not limited to, a keyboard, amouse, a touchpad, a microphone, a display, a touchscreen display, anaudio speaker, or the like.

The ordering module 208 may be configured to receive the dataidentifying the digital and/or analog components within the circuit andorder the components based on a topological sorting algorithm. Inparticular, the ordering module 208 may order the digital and/or analogcomponents within the circuit based on a data flow within the circuit.The digital and/or analog components that are first in the data flow maybe ordered before the digital and/or analog components that are last inthe data flow.

The constraint module 210 may be configured receive the circuitconstraints and/or other analog-component-specific constraints from theinterface module 240. The constraint module 210 may also be configuredto determine ordering constraints for each analog component based on theordering of the analog components. The ordering constraints may be basedon constraints that parameter values for a first analog component placeon a second analog component when the second analog component is afterthe first analog component in the order of analog components within acircuit. In some embodiments, the ordering constraints may be based onthe circuit constraints and/or other analog component specificconstraints. The constraint module 210 may also be configured to sendthe circuit constraints, other analog component specific constraints,and/or the ordering constraints to the pareto-front module 214.

The pareto-front module 214 may be configured to receive the dataidentifying the ordered digital and/or analog components from theordering module 208 and predetermined constraints and orderingconstraints from the constraint module 210. Additionally, thepareto-front module 214 may be configured to receive the low-levelmodels of the analog components from the interface module 240 or fromthe database 230.

Starting with a first analog component, and based on the order of thecomponents determined by the ordering module 208, the pareto-frontmodule 214 may be configured to determine one or more pareto-optimaldesign points additionally based on one or more of: the low level modelfor the first analog component, parameters for the first analogcomponent, performance metrics for the first analog component, circuitconstraints, ordering constraints, and constraints specific to the firstanalog component. To determine the one or more pareto-optimal designpoints, the pareto-front module 214 may perform simulations of the firstanalog component using the low-level model and varying values of theparameters to minimize or maximize the performance metrics within thecircuit constraints and/or conform to the ordering constraints and/orconstraints specific to the first analog component.

In some embodiments, the pareto-front module 214 may determine between 1and 5 pareto-optimal design points. In other embodiments, thepareto-front module 214 may determine more than 5 pareto-optimal designpoints. In some embodiments, the number of pareto-optimal design pointsto be determined by the pareto-front module 214 may be predetermined orreceived through the interface module 240. Each of the pareto-optimaldesign points may be associated with the values of the performancemetrics at the pareto-optimal design point. In some embodiments, thepareto-front module 214 may send the determined pareto-optimal designpoints and the associated performance metric values to the validationmodule 220 or store the determined pareto-optimal design points in thedatabase 230.

After the pareto-front module 214 determines the pareto-optimal designpoints for the first analog component, the pareto-front module 214 maysend the pareto-optimal design points to the constraint module 210. Theconstraint module 210 may use the pareto-optimal design points todetermine ordering constraints for the analog components following thefirst analog component. By changing the ordering constraints to reflectconstraints resulting from the pareto-optimal design points instead ofthe values of the predetermined parameters, the designing system 200 maydesign the circuit based on the interactions between the analogcomponents in the circuit. Designing the circuit based on theinteractions between the analog components in the circuit may produce abetter-optimized circuit than designing each individual analog componentin a circuit in isolation and then combining the individually designedanalog components.

In some embodiments, the pareto-front module 214 may also be configuredto determine a pareto-front for the first analog component based on thepareto-optimal design points. For example, in some embodiments, thepareto-front module 214 may use the pareto-optimal design points tointerpolate the pareto-front for the first analog component.

The validation module 220 may be configured to obtain the pareto-optimaldesign points from the pareto-front module 214 or the database 230. Foreach pareto-optimal design point, the validation module 220 may beconfigured to simulate the first analog component using the high-levelmodule of the analog component received from the interface module 240 orthe database 230 and the parameter values of the respectivepareto-optimal design point. The simulation of the first analogcomponent using the high-level module may produce performance metrics.The values of the performance metrics from the high-level module may becompared to the values of the performance metrics associated with therespective pareto-optimal design point to validate the high-levelmodule. If the values of the performance metrics from the high-levelmodule are within a predetermined tolerance of the values of theperformance metrics associated with the respective pareto-optimal designpoint, the high-level module may be validated as accurately modeling theanalog component for the respective pareto-optimal design point. In someembodiments, if the high-level module fails to be validated by one ormore of the pareto-optimal design points, the high-level module may beadjusted until it may be verified for each pareto-optimal design point.In other embodiments, if the high-level module fails to be validated byless than half or some other predetermined ratio of the pareto-optimaldesign points, the high-level module may still be verified.

After the high-level module of the first analog component is validated,the circuit simulation module 224 may be configured to simulate thecircuit using the high-level modules for each of the analog components.In particular, the circuit simulation module 224 may use the circuitconstraints, the high-level module for the first analog component usingparameter values from one of the pareto-optimal design points, andhigh-level modules for the analog components without determinedpareto-optimal design points using the predetermined parameters tosimulate the circuit. In some embodiments, the circuit simulation module224 may perform a simulation of the circuit for each of thepareto-optimal design points. In some embodiments, the designing system200 may determine, based on the one or more performance metrics for thecircuit or other considerations, which pareto-optimal design pointyields the most optimized circuit.

In some embodiments, the circuit simulation module 224 may performsimulations of the circuit to determine if the design criteria of thecircuit have been met. If the design criteria has not been met, in someembodiments, the pareto-front module 214, the validation module 220, andthe circuit simulation module 224 may perform functionality similar tothat described above with respect to the first analog component on oneor more of the remaining analog components of the circuit ordered by theordering module 208 until the design criteria is met.

In some embodiments, the circuit simulation module 224 may performsimulations of the circuit based on a pareto-front of the first analogcomponent and the parameter values thereof and predetermined parametervalues for the analog components without determined pareto-optimaldesign points. In some embodiments, the circuit simulation module 224may not perform simulations of the circuit until more than one or all ofthe analog components of the circuit have determined pareto-optimaldesign points or determined pareto-fronts. In these and otherembodiments, the pareto-front module 214 and the validation module 220may perform functionality similar to that described above with respectto the first analog component on one or more of the remaining analogcomponents of the circuit ordered by the ordering module 208. Afterpareto-optimal design points are determined for the one or moreadditional analog components, the circuit simulation module 224 mayperform simulations of the circuit.

In some embodiments, the pareto-front module 214, the validation module220, and the circuit simulation module 224 may perform functionalitysimilar to that described above with respect to the first analogcomponent on one or more of the remaining analog components of thecircuit ordered by the ordering module 208 to determine a pareto-optimalfront for the circuit.

In some embodiments, the processor 244 may be configured to executecomputer instructions that cause the designing system 200 to perform thefunctions and operations described herein. The computer instructions maybe loaded into the memory 242 for execution by the processor 244 and/ordata generated, received, or operated on during performance of thefunctions and operations described herein may be at least temporarilystored in the memory 242.

FIG. 3 is a flow chart of an example method 300 of designing analogcircuits, arranged in accordance with at least some embodimentsdescribed herein. The method 300 may be implemented, in someembodiments, by a designing system, such as the designing system 200 ofFIG. 2. For instance, the processor 244 within the designing system 200of FIG. 2 may be configured to execute computer instructions to causethe designing system 200 to perform operations for designing analogcircuits as represented by one or more of blocks 302, 306, 310, 314,318, 320, 322, 324, 328, 330, 336, 340, 344, 348, and 350 of the method300. Although illustrated as discrete blocks, various blocks may bedivided into additional blocks, combined into fewer blocks, oreliminated, depending on the desired implementation.

The method 300 may begin at block 302, in which analog components to beused within a circuit are selected. For example, the circuit may includea VCO and a CP. At block 302, the method 300 may include selecting thetype of VCO and the type of CP for use in the circuit. For example, themethod 300 may include selecting between a ring oscillator type VCO anda LC-tank oscillator type VCO for use in the circuit. In someembodiments, the circuit may include digital components as well asanalog components.

At block 306, the components within the circuit may be ordered. In someembodiments, the components may be ordered based on a topologicalsorting algorithm. In particular, the components may be ordered based ona data flow within the circuit. The first analog component within thecircuit may be given the number of 1 and the remaining ordered analogcomponents may be given corresponding numbers based on the order of theanalog components. For example, the fourth ordered analog component maybe given the number of 4. More generally, any numbering suitable toindicate an order of the analog components may be implemented.

At block 310, a component number (C_(N)) may be set to 1. The componentnumber may be a variable used by the method 300 to determine whichanalog component of the circuit is currently being designed.

At block 314, an analog component with a number equal to the componentnumber may be pushed onto a top of an operations stack and be referredto as the current analog component.

At block 318, constraints may be set for the current analog component.The constraints that are set may be obtained from one or more sources.In some embodiments, the constraints may be predetermined constraintsbased on the circuit. Alternately or additionally, the constraints maybe predetermined constraints for the current analog component.Alternately or additionally, the constraints may be constraints that arebased on pareto-optimal design points generated for analog componentsthat were ordered ahead of the current analog component.

At block 320, a pareto-optimal design point may be determined for thecurrent analog component. The pareto-optimal design point may bedetermined based on one or more predetermined performance metrics, oneor more predetermined parameters, and/or the constraints set in block318 for the current analog component, using a low-level model for thecurrent analog component. In some embodiments, multiple pareto-optimaldesign points may be generated for the current analog component.Alternately or additionally, a pareto-front may be generated for thecurrent analog component.

At block 322, it is determined if a pareto-optimal design point wasdetermined for the current analog component. In some embodiments, atblock 320, no pareto-optimal design point may be determined based on theone or more predetermined performance metrics, the one or morepredetermined parameters, and/or the constraints set in block 318 forthe current analog component. The inability to determine apareto-optimal design point may indicate that either the predeterminedconstraints or the constraints resulting from the pareto-optimal designpoints of other analog components may not be met based on thepredetermined parameters. In these circumstances, block 322 may befollowed by block 324. Block 322 may be followed by block 336 when oneor more pareto-optimal design points are determined for the currentanalog component.

At block 336, a high-level model, such as a hardware definition languagemodel, may be characterized using the pareto-optimal design pointdetermined in block 320. The high-level model may automatically begenerated through some external process or provided by a user. In someembodiments, the high-level model may be a parameterized model.Characterizing the high-level model may include populating thehigh-level model with the parameters associated with the pareto-optimaldesign point determined in block 320.

At block 340, the high-level model characterized in block 336 may bevalidated. To validate the high-level model, the high-level model may besimulated to produce performance metric values for the high-level model.The performance metric values for the high-level model may be comparedto the performance metric values associated with the pareto-optimaldesign point as determined at block 320. The high-level model may bevalidated when the performance metric values for the high-level modelare within a predetermined tolerance of the performance metric valuesassociated with the pareto-optimal design point.

At block 344, the circuit may be simulated using the high-level modulesfor each of the analog components. Analog components with a determinedpareto-optimal design point may be simulated using the pareto-optimaldesign point. Analog components without a determined pareto-optimaldesign point may be simulated using predetermined parameter values.

At block 348, it is determine if a design goal for the circuit has beenmet based on the simulation of the circuit at block 344. If the designgoal is met, the circuit may have been sufficiently optimized and themethod may proceed to block 330 where the method 300 ends. If the designgoal is not meet, the method 300 may proceed to block 350.

At block 350, the component number may be advanced by one and the method300 may proceed to block 314. When the method 300 returns to block 314,an analog component with a number, based on the ordering of the analogcomponents, equal to the component number may be pushed onto the top ofthe operations stack and set as the current analog component and themethod 300 may continue. As the method 300 continues, constraints may beset for the current analog component at block 318, a pareto-optimaldesign point may be selected for the current analog component at block320, a high-level model may be characterized for the current analogcomponent at block 336, the high-level model may be validated at block340, and the circuit may again be simulated at block 344.

When the circuit is simulated at block 344, an additional analogcomponent has a pareto-optimal design point. Having an additional analogcomponent a pareto-optimal design point may further optimize the circuitand result in the circuit meeting a design goal for the circuit.Furthermore, the pareto-optimal design point for the additional analogcomponent may be determined based on constraints resulting from thepareto-optimal design points of other analog components. Thus, eachiteration of the method 300 may take into account the optimization ofthe previous analog component and may not be simply simulating analogcomponents that are optimized through pareto-optimal design pointsindividually.

Optionally, in some embodiments, for example when the circuit includes afeedback loop, the method 300 may include block 352. At block 352, whenthe component number is not greater than the total number of analogcomponents in the circuit, the method 300 may proceed to block 314 aspreviously discussed herein. At block 352, when the component number isgreater than the total number of analog components in the circuit, themethod 300 may proceed to block 310.

At block 310, the component number may be set to 1 and in block 314 thefirst analog component based on the ordering of the analog componentsmay be set as the current analog component. In these and otherembodiments, all of the analog components from the circuit may be on thestack. As a result, the first analog component may have a pareto-optimaldesign point determined based on constraints resulting from thepareto-optimal design points of all of the other analog components inthe circuit. Determining a pareto-optimal design point based onconstraints resulting from the pareto-optimal design points of all ofthe other analog components in the circuit may result in furtheroptimization of the analog component and thus further optimization ofthe circuit.

At block 320, a pareto-optimal design point may be determined for thecurrent analog component as discussed previously.

At block 322, it is determined if a pareto-optimal design point wasdetermined for the current analog component at block 320. As discussedpreviously, block 322 may be followed by block 336 when one or morepareto-optimal design points are determined for the current analogcomponent. When no pareto-optimal design point may be determined basedon the one or more predetermined performance metrics, the one or morepredetermined parameters, and/or the constraints set in block 318 forthe current analog component, block 322 may be followed by block 324.

At block 324, the current analog component may be removed from theoperations stack. In some embodiments, removing the current analogcomponent from the operations stack may result in the operations stackbeing empty. In other embodiments, removing the current analog componentfrom the operations stack may result in an analog component below thecurrent analog component on the operations stack becoming the currentanalog component.

At block 328, it is determined if the operations stack is empty. If theoperations stack is empty, block 328 may be followed by block 330 andthe method 300 may end. If the operations stack is not empty, block 328may be followed by block 318.

At block 318, constraints may be set for the current analog componentand at block 320 a pareto-optimal design point may be selected. Thispareto-optimal design point may be different from the pareto-optimaldesign point previously selected for the current analog component. Byselecting a new pareto-optimal design point, the one or more constraintsresulting from the pareto-optimal design point may change and allow apareto-optimal design point to be determined for the analog componentfollowing the current analog component for which a pareto-optimal designpoint was not previously able to be determined.

In some embodiments, the method 300 may be repeated for differentcomponent configurations not initially selected at block 302. Theresults from using the different analog component configurations may becompared and the best component may be selected.

In some embodiments, the method 300 may be modified to determinemultiple pareto-optimal design points for each analog component within acircuit to accurately determine a pareto-front for each analogcomponent. Based on the pareto-optimal front of each component, apareto-optimal front for the circuit may also be determined. Using thepareto-optimal front for the circuit may allow for trade-offs ofperformance metrics of the circuit to be determined and analyzedallowing for a better design and/or optimization of the circuit.

FIG. 4 illustrates an example circuit 400 that may be designed using themethod 300 of FIG. 3, arranged in accordance with at least someembodiments described herein. The circuit 400 may include a phasefrequency detector (PFD) 410, a VCO 420, and a CP 430. In someembodiments, the circuit 400 may be a clock data recovery (CDR) circuit.In the circuit 400, the PFD 410 may be a digital component and the VCO420 and the CP 430 may be analog components. The method 300 may be usedto design the VCO 420 and the CP 430.

For example, and with combined reference to FIGS. 3 and 4, at block 302,analog components may be selected for the VCO 420 and the CP 430. Forexample, a ring oscillator VCO may be selected for the VCO 420 and afly-back capacitor charge pump may be selected for the CP 430. In someembodiments, the VCO 420 may have parameters such as transistor widths,inductor sizes, and capacitor sizes. The VCO 420 may also haveperformance metrics such a quality factor, jitter, area, and power. Inother embodiments, the VCO 420 may have different parameters and/ordifferent performance metrics. In some embodiments, the CP 430 may haveparameters such as transistors widths, and in particular, the widths ofthe transistors that determine the control currents for adjusting thecontrolling voltage within the CP 430. The CP 430 may also haveperformance metrics such as matching control currents, phase noise, andjitter. In other embodiments, the CP 430 may have different parametersand/or different performance metrics.

At block 306, the VCO 420 and the CP 430 may be ordered based on thetopology of the circuit 400. The CP 430 may be selected to be first andmay be given the number of 1 and the VCO 420 may follow the CP 430 andmay be given the number of 2.

At block 310, the component number is set to 1. At block 314, the CP 430is pushed onto the operation stack and becomes the current analogcomponent. At block 318, constraints are set for the CP 430. Thepredetermined constraints may include minimal voltage swings, timing forchanging the voltage, power requirements, sizing requirements, amongothers. Alternately or additionally, the constraints may be set based onthe predetermined parameter values for the VCO 420.

At block 320, a pareto-optimal design point may be determined for thetransistors widths with respect to the matching control currents, phasenoise, jitter, and the predetermined constraints using a transistorlevel model of the CP 430. To determine the pareto-optimal designpoints, various design points with varying transistor widths may be usedin the transistor level model of the CP 430 to generate the performancemetrics of the CP 430 and information about the predeterminedconstraints. Transistor widths that are determined to meet thepredetermined constraints, produce matching control currents, and reducephase noise and jitter may be set as the pareto-optimal design point.

At block 336, a high-level model may be characterized using thepareto-optimal design point determined in block 320. At block 340, thehigh-level model may be validated. At block 344, the circuit 400 may besimulated using the high-level models for the VCO 420 and the CP 430.The simulation may use a high-level model of the VCO 420 withpredetermined parameters as received by a user or from a database. Thesimulation may also use the high-level model of the CP 430 characterizedin block 336 using the pareto-optimal design point for the CP 430. Insome embodiments, the design goal may be met at block 348. If the designgoal is not met, at block 350, the component number is set to 2.

At block 314, the VCO 420 is pushed onto the stack and becomes thecurrent analog component. At block 318, constraints are set for the VCO420. The predetermined constraints may include minimal voltage swings,timing for changing the voltage, power requirements, sizingrequirements, among others. Additional constraints may also be set basedon the pareto-optimal design point selected for the CP 430. For example,an additional constraint, such as an input impedance for the VCO 420 maybe set based on the pareto-optimal design point for the CP 430.

At block 320, a pareto-optimal design point may be determined for thetransistor widths, inductor sizes, and capacitor sizes with respect tothe quality factor, jitter, area, and power of the VCO 420 and theconstraints set at block 318 using a transistor level model of the VCO420. To determine the pareto-optimal design points, various designpoints with varying transistor widths, inductor sizes, and capacitorsizes may be used in the transistor level model of the VCO 420 togenerate the performance metrics of the VCO 420 and information aboutthe set constraints. Transistor widths, inductor sizes, and capacitorsizes that are determined to meet the set constraints and produceoptimizations for the quality factor, jitter, area, and power may be setas the pareto-optimal design point.

At block 336, a high-level model may be characterized using thepareto-optimal design point determined in block 320. At block 340, thehigh-level model may be validated. At block 344, the circuit 400 may besimulated using the high-level models for the VCO 420 and the CP 430.The simulation may use the characterized high-level model of the VCO 420with the determined pareto-optimal design point of the VCO 420. Thesimulation may also use the high-level model of the CP 430 with thedetermined pareto-optimal design point of the CP 430. In someembodiments, the design goal may be met at block 348. If the design goalis not met, at block 350, the component number may be set to 3 andbecause the component number is greater than the number of analogcomponents in the circuit 400, the method 300 may proceed to block 310and the component number may be set to 1.

The method 300 may proceed as previously indicated, however, during thisiteration, the constraints set at block 318 may result from thepareto-optimal design point determined for the VCO 420. By havingpareto-optimal design points selected twice for the CP 430, the method300 may take into account that the circuit 400 has a feedback loop.

FIG. 5 is a flow chart of an example method 500 of designing analogcircuits, arranged in accordance with at least some embodimentsdescribed herein. The method 500 may be implemented, in someembodiments, by an optimization system, such as the designing system 200of FIG. 2. For instance, the processor 244 within the designing system200 of FIG. 2 may be configured to execute computer instructions tocause the designing system 200 to perform operations for designinganalog circuits as represented by one or more of blocks 502, 504, 506,and/or 508 of the method 500. Although illustrated as discrete blocks,various blocks may be divided into additional blocks, combined intofewer blocks, or eliminated, depending on the desired implementation.

The method 500 may begin at block 502, in which a first pareto-optimaldesign point may be determined for a first analog component within acircuit based on a parameter of the first analog component and aperformance metric for the first analog component. In some embodiments,the circuit may include analog components and digital components.

At block 504, a second pareto-optimal design point may be determined fora second analog component coupled to the first analog component withinthe circuit, the second pareto-optimal design point based on a parameterof the second analog component, a performance metric for the secondanalog component, and a first constraint resulting from the firstpareto-optimal design point.

At block 506, a third pareto-optimal design point may be determined forthe first analog component based on the performance metric for the firstanalog component and a second constraint resulting from the secondpareto-optimal design point. In some embodiments, the firstpareto-optimal design point, the second pareto-optimal design point, andthe third pareto-optimal design point may be determined using transistorlevel modeling.

At block 508, a value may be selected for the first parameter of thefirst analog component at least partially based on the thirdpareto-optimal design point.

One skilled in the art will appreciate that, for this and otherprocesses and methods disclosed herein, the functions performed in theprocesses and methods may be implemented in differing order.Furthermore, the outlined steps and operations are only provided asexamples, and some of the steps and operations may be optional, combinedinto fewer steps and operations, or expanded into additional steps andoperations without detracting from the essence of the disclosedembodiments.

For instance, the method 500 may further include characterizing ahardware language model of the second analog component based on thesecond pareto-optimal design point. Alternately or additionally, themethod 500 may further include characterizing a hardware language modelof the first analog component based on the third pareto-optimal designpoint.

In some embodiments, the method 500 may further include simulating thecircuit based on the hardware language model of the first analogcomponent and the hardware language model of the second analogcomponent. Alternately or additionally, the method 500 may furtherinclude validating the hardware language model of the second analogcomponent using the second pareto-optimal design point.

The embodiments described herein may include the use of a specialpurpose or general-purpose computer including various computer hardwareor software modules, as discussed in greater detail below.

Embodiments described herein may be implemented using computer-readablemedia for carrying or having computer-executable instructions or datastructures stored thereon. Such computer-readable media may be anyavailable media that may be accessed by a general purpose or specialpurpose computer. By way of example, and not limitation, suchcomputer-readable media may comprise tangible computer-readable mediaincluding RAM, ROM, EEPROM, CD-ROM or other optical disk storage,magnetic disk storage or other magnetic storage devices, or any othermedium which may be used to carry or store desired program code in theform of computer-executable instructions or data structures and whichmay be accessed by a general purpose or special purpose computer.Combinations of the above may also be included within the scope ofcomputer-readable media.

Computer-executable instructions comprise, for example, instructions anddata which cause a general purpose computer, special purpose computer,or special purpose processing device to perform a certain function orgroup of functions. Although the subject matter has been described inlanguage specific to structural features and/or methodological acts, itis to be understood that the subject matter defined in the appendedclaims is not necessarily limited to the specific features or actsdescribed above. Rather, the specific features and acts described aboveare disclosed as example forms of implementing the claims.

As used herein, the term “module” or “component” may refer to softwareobjects or routines that execute on the computing system. The differentcomponents, modules, engines, and services described herein may beimplemented as objects or processes that execute on the computing system(e.g., as separate threads). While the system and methods describedherein are preferably implemented in software, implementations inhardware or a combination of software and hardware are also possible andcontemplated. In this description, a “computing entity” may be anycomputing system as previously defined herein, or any module orcombination of modulates running on a computing system.

All examples and conditional language recited herein are intended forpedagogical objects to aid the reader in understanding the invention andthe concepts contributed by the inventor to furthering the art, and areto be construed as being without limitation to such specifically recitedexamples and conditions. Although embodiments of the present inventionshave been described in detail, it should be understood that the variouschanges, substitutions, and alterations could be made hereto withoutdeparting from the spirit and scope of the invention.

What is claimed is:
 1. A method of designing an analog circuit, themethod comprising: determining a first pareto-optimal design point for afirst analog component within a circuit based on a parameter of thefirst analog component and a performance metric for the first analogcomponent using a first simulation of a low level modeling simulationtype; determining, using a processor, a second pareto-optimal designpoint for a second analog component using a second simulation thatexcludes the first analog component, the second simulation being of thelow level modeling simulation type used for the first simulation, thesecond analog component being coupled to the first analog componentwithin the circuit and the second pareto-optimal design point beingbased on a parameter of the second analog component, a performancemetric for the second analog component, and a first constraint resultingfrom the first pareto-optimal design point; and selecting a first valuefor the parameter of the first analog component at least partially basedon the first pareto-optimal design point.
 2. The method of claim 1,wherein the low level modeling simulation type is based on transistorlevel modeling.
 3. The method of claim 1, further comprisingcharacterizing a hardware language model of the second analog componentbased on the second pareto-optimal design point.
 4. The method of claim3, further comprising characterizing a hardware language model of thefirst analog component based on the first pareto-optimal design point.5. The method of claim 4, further comprising simulating the circuitbased on the hardware language model of the first analog component andthe hardware language model of the second analog component.
 6. Themethod of claim 3, further comprising validating the hardware languagemodel of the second analog component using the second pareto-optimaldesign point.
 7. The method of claim 1, further comprising: determininga third pareto-optimal design point for the first analog component basedon the performance metric for the first analog component and a secondconstraint resulting from the second pareto-optimal design point; andselecting a second value for the parameter of the first analog componentat least partially based on the third pareto-optimal design point.
 8. Amethod of designing an analog circuit, the method comprising: selectinga plurality of analog components for a circuit; ordering the analogcomponents; determining, using a processor, at least one pareto-optimaldesign point for a parameter of each analog component using a simulationof a low-level model of each analog component, the simulation used foreach of the respective analog components being of the same low levelmodeling simulation type, the pareto-optimal design point for eachanalog component being based on a performance metric, the parameter forthe respective analog component, and constraints resulting frompareto-optimal design points for analog components ahead of therespective analog component within the ordering of the analogcomponents; and characterizing a high-level model for each of the analogcomponents based on the pareto-optimal design point of the respectiveanalog component.
 9. The method of claim 8, wherein the low-level modelis a transistor level model.
 10. The method of claim 8, wherein theanalog components are ordered based on a topological order of thecircuit.
 11. The method of claim 8, wherein the high-level model is ahardware language model.
 12. The method of claim 11, further comprisingvalidating the hardware language model for each of the analog componentsbased on the pareto-optimal design point for the respective analogcomponent.
 13. The method of claim 11, further comprising simulating thecircuit based on the hardware language model of each of the analogcomponents.
 14. The method of claim 8, wherein the circuit comprisesanalog components and digital components.
 15. A processor configured toexecute computer instructions stored in a computer-readable storagemedium to cause a system to perform operations for designing an analogcircuit, the operations comprising: selecting a plurality of analogcomponents for a circuit; ordering the analog components; determining atleast one pareto-optimal design point for a parameter of each analogcomponent using a simulation of a low-level model of each analogcomponent, the simulation used for each of the respective analogcomponents being of the same low level modeling simulation type, thepareto-optimal design point for each analog component being based on aperformance metric, the parameter for the respective analog component,and constraints resulting from pareto-optimal design points for analogcomponents ahead of the respective analog component within the orderingof the analog components; and characterizing a high-level model for eachof the analog components based on the pareto-optimal design point forthe respective analog component.
 16. The processor of claim 15, whereinthe low-level model is a transistor level model.
 17. The processor ofclaim 15, wherein the high-level model is a hardware language model. 18.The processor of claim 17, wherein the operations further comprisesimulating the circuit based on the hardware language model of each ofthe analog components.
 19. The processor of claim 17, wherein theoperations further comprise validating the hardware language model foreach of the analog components based on the pareto-optimal design pointfor the respective analog component.
 20. The processor of claim 15,wherein the circuit comprises analog components and digital components.